diff --git a/.gitignore b/.gitignore index 358cadf..ad7b942 100644 --- a/.gitignore +++ b/.gitignore @@ -1,4 +1,5 @@ bootloader/build/* lark1fq/build/* +test/build/* .vscode/* diff --git a/test/CMakeLists.txt b/test/CMakeLists.txt new file mode 100755 index 0000000..7f0356c --- /dev/null +++ b/test/CMakeLists.txt @@ -0,0 +1,44 @@ +cmake_minimum_required(VERSION 3.10) +set(PROJ_NAME "test") +set(BIN_FILE ${PROJ_NAME}.bin) +set(ASM_FILE ${PROJ_NAME}.asm) +project(${PROJ_NAME} VERSION 0.1) + +# toolchain path +set(TOOLCHAIN "arm-none-eabi-") +set(CMAKE_C_COMPILER "${TOOLCHAIN}gcc") +set(CMAKE_ASM_COMPILER "${TOOLCHAIN}gcc") +set(CMAKE_OBJCOPY "${TOOLCHAIN}objcopy") +set(CMAKE_OBJDUMP "${TOOLCHAIN}objdump") +set(CMAKE_AR "${TOOLCHAIN}ar") +set(CMAKE_RANLIB "${TOOLCHAIN}ranlib") +set(LINKER_SCRIPT "${CMAKE_CURRENT_SOURCE_DIR}/flash.ld") + +set(MCU_FLAGS "-mcpu=cortex-m4 -mthumb -g -O2 -Wall -nostartfiles -mfloat-abi=hard -mfpu=vfpv4-d16 -ffunction-sections -fdata-sections") +set(CMAKE_C_FLAGS "${MCU_FLAGS}") +set(CMAKE_ASM_FLAGS "${MCU_FLAGS}") +set(CMAKE_EXE_LINKER_FLAGS "${MCU_FLAGS} -T${LINKER_SCRIPT} -Wl,-Map=test.map") + +add_definitions(-DSTM32F40_41xxx) +add_definitions(-DUSE_STDPERIPH_DRIVER) + +enable_language(ASM) +add_executable(${PROJ_NAME}.elf main.c) +target_sources(${PROJ_NAME}.elf PUBLIC start.S) + +add_subdirectory(../driver driver) +target_link_libraries(${PROJ_NAME}.elf driver) +target_include_directories(${PROJ_NAME}.elf PUBLIC ../driver/stddriver/inc) +target_include_directories(${PROJ_NAME}.elf PUBLIC ../driver/cmsis/inc) + +add_subdirectory(src src) +target_link_libraries(${PROJ_NAME}.elf src) +target_include_directories(${PROJ_NAME}.elf PUBLIC src) + +target_link_libraries(${PROJ_NAME}.elf m) # math library + +add_custom_command(TARGET ${PROJ_NAME}.elf POST_BUILD + COMMAND ${CMAKE_OBJCOPY} -Obinary $ ${BIN_FILE} + COMMAND ${CMAKE_OBJDUMP} -d -S $ >${ASM_FILE} + COMMENT "Generate ${BIN_FILE}\r\n" +) diff --git a/test/flash.ld b/test/flash.ld new file mode 100755 index 0000000..b7736c5 --- /dev/null +++ b/test/flash.ld @@ -0,0 +1,79 @@ +ENTRY(Reset_Handler) + +MEMORY +{ + FLASH (rx) :ORIGIN = 0x08020000, LENGTH = 384K + RAM (xrw) :ORIGIN = 0x20000000, LENGTH = 112K + CCM (rw) :ORIGIN = 0x10000000, LENGTH = 48K + CCM_STACK (rw) :ORIGIN = 0x1000C000, LENGTH = 16K +} + +_stack_top = ORIGIN(CCM_STACK) + LENGTH(CCM_STACK); + +SECTIONS +{ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) + . = ALIGN(4); + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + . = ALIGN(4); + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + _data_load = LOADADDR(.data); + .data : + { + . = ALIGN(4); + _data_run = .; + *(.data) + *(.data.*) + . = ALIGN(4); + _data_run_end = .; + } >RAM AT>FLASH + + _data_ccm_load = LOADADDR(.data_ccm); + .data_ccm : + { + . = ALIGN(4); + _data_ccm_run = .; + *(.data_ccm) + *(.data_ccm*) + . = ALIGN(4); + _data_ccm_run_end = .; + } >CCM AT>FLASH + + .bss (NOLOAD) : + { + . = ALIGN(4); + _bss_run = .; + *(.bss) + *(.bss.*) + . = ALIGN(4); + _bss_run_end = .; + } >RAM + + .bss_ccm (NOLOAD) : + { + . = ALIGN(4); + _bss_ccm_run = .; + *(.bss_ccm) + *(.bss_ccm.*) + . = ALIGN(4); + _bss_ccm_run_end = .; + } >CCM +} diff --git a/test/main.c b/test/main.c new file mode 100755 index 0000000..57abd1e --- /dev/null +++ b/test/main.c @@ -0,0 +1,39 @@ +#include "ltc1867.h" +#include "debug.h" +#include "stm32f4xx_rcc.h" + +uint32_t system_tick_cnt; + +void system_tick_init(void) +{ + RCC_ClocksTypeDef rcc_clocks; + + system_tick_cnt = 0; + RCC_GetClocksFreq(&rcc_clocks); + SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK); + SysTick_Config(rcc_clocks.HCLK_Frequency / 1000); +} + +void system_init(void) +{ + ltc1867_init(); + debug_init(); + system_tick_init(); +} + +int main(void) +{ + system_init(); + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4); + SCB->VTOR = 0x08020000; + __enable_irq(); + while (1) { + + } + return 0; +} + +void SysTick_Handler(void) +{ + system_tick_cnt++; +} diff --git a/test/src/CMakeLists.txt b/test/src/CMakeLists.txt new file mode 100755 index 0000000..da62273 --- /dev/null +++ b/test/src/CMakeLists.txt @@ -0,0 +1,11 @@ +file(GLOB FILELIST +ltc1867.c +debug.c +) + +include_directories(.) +include_directories(../../driver/stddriver/inc) +include_directories(../../driver/cmsis/inc) + +add_library(src STATIC ${FILELIST}) +target_link_libraries(src driver) diff --git a/test/src/debug.c b/test/src/debug.c new file mode 100755 index 0000000..d705be3 --- /dev/null +++ b/test/src/debug.c @@ -0,0 +1,100 @@ +#include "debug.h" +#include "stm32f4xx_rcc.h" +#include "stm32f4xx_gpio.h" +#include "stm32f4xx_usart.h" +#include "stm32f4xx_dma.h" + +struct debug_data_s debug_data; +float debug_buff[DEBUG_CHAN_MAX + 1] __attribute__((aligned(16))); + +void debug_init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + USART_InitTypeDef USART_InitStructure; + DMA_InitTypeDef DMA_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + + /* config debug uart pin */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE); + GPIO_PinAFConfig(DEBUG_UART_PORT, GPIO_PinSource6, GPIO_AF_USART6); + GPIO_InitStructure.GPIO_Pin = DEBUG_UART_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(DEBUG_UART_PORT, &GPIO_InitStructure); + /* config debug uart function */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE); + USART_DeInit(USART6); + USART_OverSampling8Cmd(USART6, DISABLE); + USART_InitStructure.USART_BaudRate = DEBUG_UART_BAUDRATE; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Tx; + USART_Init(USART6, &USART_InitStructure); + USART_DMACmd(USART6, USART_DMAReq_Tx, ENABLE); + USART_Cmd(USART6, ENABLE); + /* Configure DMA controller to manage UART TX request */ + DMA_InitStructure.DMA_BufferSize = DEBUG_CHAN_MAX * 4 + 4; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + DMA_InitStructure.DMA_PeripheralBaseAddr =(uint32_t)(&(USART6->DR)); + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_Priority = DMA_Priority_Low; + DMA_InitStructure.DMA_Channel = DMA_Channel_5; + DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)debug_buff; + DMA_Init(DMA2_Stream6, &DMA_InitStructure); + /* Configure interrupt for USART6 TX */ + NVIC_InitStructure.NVIC_IRQChannel = USART6_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 10; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + USART_ITConfig(USART6, USART_IT_TC, ENABLE); + + /* debug data init */ + debug_data.enable = DEBUG_ENABLE; + debug_data.busy = 0; +} + +void debug_send_frame(void) +{ + if (debug_data.enable == 0 || debug_data.busy == 1) { + return; + } + debug_data.busy = 1; + *(uint32_t *)(debug_buff + DEBUG_CHAN_MAX) = 0x7F800000; + DMA_SetCurrDataCounter(DMA2_Stream6, sizeof(debug_buff)); + USART_ClearITPendingBit(USART6, USART_IT_TC); + DMA_Cmd(DMA2_Stream6, ENABLE); +} + +void debug_write_data(uint16_t ch, float data) +{ + if (debug_data.enable == 0) { + return; + } + if (ch >= DEBUG_CHAN_MAX) { + while (1) {} + } + debug_buff[ch] = data; +} + +void USART6_IRQHandler(void) +{ + if (USART_GetITStatus(USART6, USART_IT_TC) != RESET) { + USART_ClearITPendingBit(USART6, USART_IT_TC); + DMA_ClearFlag(DMA2_Stream6, DMA_FLAG_TCIF6); + debug_data.busy = 0; + } +} diff --git a/test/src/debug.h b/test/src/debug.h new file mode 100755 index 0000000..4e4b0cb --- /dev/null +++ b/test/src/debug.h @@ -0,0 +1,34 @@ +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "stm32f4xx.h" + +#define DEBUG_ENABLE (1) + +#define DEBUG_UART_PORT (GPIOC) +#define DEBUG_UART_PIN (GPIO_Pin_6) +#define DEBUG_UART_BAUDRATE (2 * 1000 * 1000) + +#define DEBUG_CH_RAW (0) +#define DEBUG_CHAN_MAX (1) + +struct debug_data_s { + uint8_t enable; + uint8_t busy; +}; + +extern struct debug_data_s debug_data; + +void debug_init(void); +void debug_send_frame(void); +void debug_write_data(uint16_t ch, float data); + +#ifdef __cplusplus +} +#endif + +#endif /* __DEBUG_H__ */ diff --git a/test/src/ltc1867.c b/test/src/ltc1867.c new file mode 100755 index 0000000..2f7a97f --- /dev/null +++ b/test/src/ltc1867.c @@ -0,0 +1,167 @@ +#include "stm32f4xx_rcc.h" +#include "stm32f4xx_gpio.h" +#include "stm32f4xx_tim.h" +#include "stm32f4xx_spi.h" +#include "ltc1867.h" +#include "debug.h" + +void ltc1867_init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; + TIM_OCInitTypeDef TIM_OCInitStructure; + SPI_InitTypeDef SPI_InitStructure; + + /* TIM3 16bit for IRLED and sample */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE); + NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + /* Time base configuration */ + TIM_TimeBaseStructure.TIM_Period = 65535; + TIM_TimeBaseStructure.TIM_Prescaler = TIMER_SRC_FREQ / LEDIR_FREQ / 65536 - 1; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure); + TIM_ARRPreloadConfig(TIM3, ENABLE); + /* TIM3 channel3 pwm output */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = 32768; + TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OC3Init(TIM3, &TIM_OCInitStructure); + TIM_OC3PreloadConfig(TIM3, TIM_OCPreload_Enable); + /* TIM3 channel4 for sample interval */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStructure.TIM_Pulse = 0; + TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low; + TIM_OC4Init(TIM3, &TIM_OCInitStructure); + TIM_OC4PreloadConfig(TIM3, TIM_OCPreload_Disable); + TIM_ITConfig(TIM3, TIM_IT_CC4, ENABLE); + /* TIM2 enable counter */ + TIM_Cmd(TIM3, ENABLE); + + /* TIM4 16bit for ADC conversion */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE); + /* Time base configuration */ + TIM_TimeBaseStructure.TIM_Period = TIMER_PERIOD_DELAY; + TIM_TimeBaseStructure.TIM_Prescaler = 0; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure); + /* Prescaler configuration */ + TIM_PrescalerConfig(TIM4, 0, TIM_PSCReloadMode_Immediate); + /* TIM4 disable counter, start when ltc1867 need delay */ + TIM_Cmd(TIM4, DISABLE); + + /* LEDIR pin configure */ + GPIO_InitStructure.GPIO_Pin = PIN_LEDIR; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE); + GPIO_Init(PORT_LEDIR, &GPIO_InitStructure); + GPIO_PinAFConfig(PORT_LEDIR, GPIO_PinSource0, GPIO_AF_TIM3); + + /* LTC1867 conv pin configure */ + GPIO_InitStructure.GPIO_Pin = PIN_CONV; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); + GPIO_Init(PORT_LTC1867, &GPIO_InitStructure); + /* config SPI for LTC1867 communication */ + GPIO_PinAFConfig(PORT_SPI, GPIO_PinSource5, GPIO_AF_SPI1); + GPIO_PinAFConfig(PORT_SPI, GPIO_PinSource6, GPIO_AF_SPI1); + GPIO_PinAFConfig(PORT_SPI, GPIO_PinSource7, GPIO_AF_SPI1); + GPIO_InitStructure.GPIO_Pin = PIN_SPI_SCK | PIN_SPI_SDI | PIN_SPI_SDO; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; + GPIO_Init(PORT_SPI, &GPIO_InitStructure); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE); + SPI_I2S_DeInit(SPI1); + SPI_InitStructure.SPI_Mode = SPI_Mode_Master; + SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b; + SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; + SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; + SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; + SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_16; + SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStructure.SPI_CRCPolynomial = 7; + SPI_Init(SPI1, &SPI_InitStructure); + SPI_Cmd(SPI1, ENABLE); + // ltc1867_spi_select(); + // ltc1867_transfer(ltc1867_spi_data[LTC1867_CH_CNT - 1]); +} + +void ltc1867_delay(void) +{ + FlagStatus sts; + + TIM_SetCounter(TIM4, 0); + TIM_ClearFlag(TIM4, TIM_FLAG_Update); + TIM_Cmd(TIM4, ENABLE); + while (1) { + sts = TIM_GetFlagStatus(TIM4, TIM_FLAG_Update); + if (sts != RESET) { + break; + } + } + TIM_Cmd(TIM4, DISABLE); +} + +void ltc1867_conv(void) +{ + GPIO_SetBits(PORT_LTC1867, PIN_CONV); +} + +void ltc1867_spi_select(void) +{ + GPIO_ResetBits(PORT_LTC1867, PIN_SPI_CS); +} + +uint16_t ltc1867_transfer(uint16_t data_send) +{ + FlagStatus flag; + + while (1) { + flag = SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_TXE); + if (flag != RESET) { + break; + } + } + SPI_I2S_SendData(SPI1, data_send); + while (1) { + flag = SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_RXNE); + if (flag != RESET) { + break; + } + } + return SPI_I2S_ReceiveData(SPI1); +} + +void TIM3_IRQHandler(void) +{ + uint16_t val_spi, val_tim; + + ltc1867_conv(); /* this point start convert */ + ltc1867_delay(); /* delay 3.5us for convert time, reference for LTC1867 datasheet */ + ltc1867_spi_select(); /* convert complete, make convert pin low for reading sample data by SPI */ + val_spi = ltc1867_transfer(0x8400); /* read convert data and send next channel information */ + + TIM_ClearITPendingBit(TIM3, TIM_IT_CC4); + val_tim = TIM_GetCapture4(TIM3); + TIM_SetCompare4(TIM3, val_tim + TIMER_INTERVAL); + + debug_write_data(0, (float)val_spi); + debug_send_frame(); +} diff --git a/test/src/ltc1867.h b/test/src/ltc1867.h new file mode 100755 index 0000000..c8e113a --- /dev/null +++ b/test/src/ltc1867.h @@ -0,0 +1,35 @@ +#ifndef __LTC1867_H__ +#define __LTC1867_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "stm32f4xx.h" + +#define LEDIR_FREQ (8) +#define TIMER_SRC_FREQ (84 * 1000 * 1000) +#define TIMER_PERIOD_DELAY (TIMER_SRC_FREQ / 1000 / 1000 * 35 / 10 - 1) /* 3.5us */ +#define TIMER_INTERVAL (32) + +#define PORT_LEDIR (GPIOB) +#define PIN_LEDIR (GPIO_Pin_0) +#define PORT_LTC1867 (GPIOA) +#define PIN_CONV (GPIO_Pin_4) +#define PORT_SPI (GPIOA) +#define PIN_SPI_CS (GPIO_Pin_4) +#define PIN_SPI_SCK (GPIO_Pin_5) +#define PIN_SPI_SDO (GPIO_Pin_6) +#define PIN_SPI_SDI (GPIO_Pin_7) + +void ltc1867_init(void); +void ltc1867_delay(void); +void ltc1867_conv(void); +void ltc1867_spi_select(void); +uint16_t ltc1867_transfer(uint16_t data_send); + +#ifdef __cplusplus +} +#endif + +#endif /* __LTC1867_H__ */ diff --git a/test/start.S b/test/start.S new file mode 100755 index 0000000..f5f4379 --- /dev/null +++ b/test/start.S @@ -0,0 +1,359 @@ +.syntax unified +.cpu cortex-m4 +.thumb + +.global g_pfnVectors +.global Default_Handler +.global Reset_Handler + +.section .text.Reset_Handler +.weak Reset_Handler +.type Reset_Handler, %function +Reset_Handler: + cpsid i /* disable irq */ + ldr r0, =_stack_top + msr msp, r0 + /* load data section */ + ldr r0, =_data_load + ldr r1, =_data_run + ldr r2, =_data_run_end + cmp r1, r2 + bhs 2f +1: + ldr r3, [r0], #4 + str r3, [r1], #4 + cmp r1, r2 + blo 1b +2: + /* clear bss section */ + ldr r0, =0 + ldr r1, =_bss_run + ldr r2, =_bss_run_end + cmp r1, r2 + bhs 2f +1: + str r0, [r1], #4 + cmp r1, r2 + blo 1b +2: + /* load data_ccm section */ + ldr r0, =_data_ccm_load + ldr r1, =_data_ccm_run + ldr r2, =_data_ccm_run_end + cmp r1, r2 + bhs 2f +1: + ldr r3, [r0], #4 + str r3, [r1], #4 + cmp r1, r2 + blo 1b +2: + /* clear bss_ccm section */ + ldr r0, =0 + ldr r1, =_bss_ccm_run + ldr r2, =_bss_ccm_run_end + cmp r1, r2 + bhs 2f +1: + str r0, [r1], #4 + cmp r1, r2 + blo 1b +2: + bl SystemInit + bl main + b . +.size Reset_Handler, .-Reset_Handler + +.section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop +.size Default_Handler, .-Default_Handler + +.section .isr_vector,"a",%progbits +.type g_pfnVectors, %object +.size g_pfnVectors, .-g_pfnVectors +g_pfnVectors: + .word _stack_top + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FSMC_IRQHandler /* FSMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word CRYP_IRQHandler /* CRYP crypto */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + .word FPU_IRQHandler /* FPU */ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + /* External Interrupts */ + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler